The present invention relates to a sputtering target and a method of manufacturing a semiconductor device.
Large-scale integrated circuits (LSIs), each incorporating a number of transistors, resistors and the like which are connected, forming electric circuits on a single chip, are widely used as major components of an electronic apparatus such as a computer or a communications apparatus. The performance of the electronic apparatus largely depends on the performance of each LSI. The performance of an LSI can be enhanced by increasing the integration density, or by minimizing the size of each circuit element.
To minimizing the size of a circuit elements, e.g., a MOS field-effect transistor (hereinafter referred to as "MOS transistor"), it is necessary to reduce the gate length and the thickness of the source/drain diffusion layer.
Known as a method of forming a shallow source-drain diffusion layer is low-acceleration ion implantation. This method can form a shallow source/drain diffusion layer as thin as 0.1 .mu.m or less.
However, a source/drain diffusion layer formed by the low-acceleration ion implantation has a sheet resistance of 100 .OMEGA./.quadrature. or more. If a circuit element has so high a sheet resistance, it cannot operate at high speed. To enable the element to operate at high speed, a recently developed method called "salicidation" may be employed. In this method, a silicide layer is deposited in self-aligned fashion on the surface of the source/drain diffusion layer.
FIGS. 1A to 1C are cross-sectional views, explaining a method of manufacturing a MOS transistor of LDD (Lightly-Doped Drain) structure, which includes a salicidation process.
First, an element isolating insulation layer 82 in the upper surface of a silicon substrate 81, defining an element forming region in the surface of the substrate 81. A gate insulation film 83 and a gate electrode 84 made of polycrystalline silicon, are formed on the element forming region. Then, using the gate electrode 84 as a mask, impurity ions are implanted into the exposed surface of the substrate 81. The resultant structure is annealed, activating the impurity ions. A lightly-dosed source/drain diffusion (LDD) layer 86b is thereby formed in the surface of the substrate 81.
Next, gate side wall insulation layers 85 having a width of about 50 nm is formed on the sides of the gate electrode 84. Using the gate side wall insulation layers 85 and the gate electrode 84 as a mask, impurity ions are implanted into the exposed surface of the substrate 81. At the same time, impurity ions are implanted into polycrystalline silicon constituting the gage electrode 84. The resultant structure is annealed, activating the impurity ions. A highly-dosed source/drain diffusion layer 86b is thereby formed. The manufacturing steps thus far performed are identical to the steps of a method of manufacturing a MOS transistor of ordinary LDD structure.
Further, as shown in FIG. 1A, a cobalt (Co) film 87 about 20 to 30 nm thick is deposited on the entire surface of the substrate 81 by means of sputtering. The resultant structure is then subjected to lamp annealing in a nitrogen atmosphere at 500 to 600.degree. C. for 30 to 60 seconds. The Co film 87 reacts with the silicon substrate 81 and also with the gate electrode 84 made of polycrystalline silicon. As a result, a cobalt silicide (CoSi) layer 88 is formed on the silicon substrate 81 and the gate electrode (polycrystalline silicon) 84 as is shown in FIG. 1B.
Unreacted part of the Co film 87 is removed by etching. The resultant structure is heated at 750 to 900.degree. C. for 30 to 60 seconds. The CoSi layer 88 formed on the source/drain diffusion layer 86b and the CoSi layer 88 formed on the gate electrode 84 are thereby changed to CoSi.sub.2 layers 88'.
An interlayer insulating layer 89 is formed on the entire surface of the substrate having the CoSi.sub.2 layers 88' on it. Contact holes are made in the interlayer insulating layer 89, thereby exposing the CoSi.sub.2 layers 88' which are formed on the source/drain diffusion layer 86b and the gate electrode 84, respectively.
Finally, source/drain electrode wires 90.sub.SD and a gate electrode wire 90.sub.G are formed, the former contacting the CoSi.sub.2 layer 88' formed on the source/drain diffusion layer 86b, and the latter contacting the CoSi.sub.2 layer 88' formed on the gate electrode 84. A MOS transistor is thus manufactured which has the LDD structure shown in FIG. 1C.
The CoSi.sub.2 layer 88' formed on the source/drain diffusion layer 86a has a thickness of about 70 to 100 nm. This layer 88' has a low sheet resistance of 2 to 3 .OMEGA./.quadrature.. Nonetheless, the method of manufacturing a MOS transistor, which includes a salicidation process, has the following disadvantages.
The first disadvantage resides in the step of depositing the Co film 87 by sputtering. Since cobalt is magnetic material, the magnetic field generated by a magnet mounted on the cathode is confined in the Co target when the Co target is sputtered by means of commonly used magnetron sputtering. Hence, it is practically impossible to generate a magnetic field on the Co target to achieve densification of plasma. In the case of Ar plasma, no discharge will occur even if the Ar pressure is raised to 1.5 Pa or more.
To eliminate the first disadvantage, the thickness of the Co target may be reduced to 3 mm or less, making it possible to generate a magnetic field at a position remote from the surface of the Co target. If the thickness of the Co target is so reduced, however, the discharge current decreases to less than 1A. Consequently, stable sputtering can hardly be performed to form Co films.
Further, if the Co target is only 3 or less mm thick, it is used up quickly when sputtering is carried out. In this case, Co targets must be replaced, each with the next one, very frequently. This inevitably lowers the operating efficiency of the sputtering apparatus. Even if the Co target is made so thin, cobalt will be deposited on the peripheral jigs such as grounding seals surrounding the target and the cathode and will affect the control of the magnetic field of the cathode. In other words, the cobalt deposited changes the magnetic field generated over the surface of the Co target. As a result, the thickness and crystalline property of the Co film 87 formed on the silicon substrate 81 will deviate from the design values. When Co films are formed on two or more silicon substrates, the thickness and crystalline property of the Co film will deviate between substrates.
The second disadvantage resides in the roughness observed at the interface between the CoSi.sub.2 layer 88' and the source/drain diffusion layer 86b. The roughness is as much as the thickness of the CoSi.sub.2 layer 88' or is almost half the thickness of the layer 88'. Inevitably, the leakage current at the pn junction increases. Namely, it is difficult to form a CoSi.sub.2 layer on a shallow source/drain diffusion layer 86b, which provides a flat interface between itself and the diffusion layer 86b. There appear to be two causes of the roughness. First, the CoSi.sub.2 layer 88' consumes and extends into the source/drain diffusion layer 86b to a depth nearly equal to the thickness of the CoSi.sub.2 layer 88'. Second, a contaminant (e.g., an oxide film naturally formed), if any, on the source/drain diffusion layer 86b results in unstable reaction between Co and Si.
The first cause may be eliminated by decreasing the thickness of the CoSi.sub.2 layer 88'. If the layer 88' is made thinner, however, the surface area per volume of the layer 88' will increase. CoSi.sub.2 tends to agglomerate to reduce the surface energy of the layer 88'. The first cause of the roughness cannot be eliminated by merely rendering the CoSi.sub.2 layer 88' thinner.
The second cause may be removed by forming a thin titanium (Ti) film on the lower surface of the Co film 87. In this case, an intermediate film containing Ti, Si and Co is formed in the initial phase of reaction between the Co film 87 and the source/drain diffusion layer 86b. Co may then be applied to the diffusion layer 86b through the intermediate film, thereby to form a CoSi.sub.2 layer which has a relatively uniform thickness. If the Ti film is too thin, however, the second cause cannot be eliminated. Conversely, if the Ti film is too thick, mixture of TiSi.sub.2 and CoSi.sub.2 is formed on the source/drain diffusion layer 86b. The mixture increases the sheet resistance of the layer 86b. An optimal value for the thickness of such a Ti film is reported to be about 5 to 10 nm. To form a Ti film having a thickness falling within this range, the process must be controlled with high accuracy. In view of this, it is not practical to use a Ti film to eliminate the second cause of the above-mentioned roughness.